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DS87C530/DS83C530 EPROM/ROM Micro with Real Time Clock
www.dalsemi.com
FEATURES
80C52-compatible - 8051 instruction set-compatible - Four 8-bit I/O ports - Three 16-bit timer/counters - 256 bytes scratchpad RAM Large on-chip memory - 16 kB EPROM (OTP) - 1 kB extra on-chip SRAM for MOVX ROMSIZE Feature - Selects effective on-chip ROM size from 0 to 16kB - Allows access to entire external memory map - Dynamically adjustable by software - Useful as boot block for external Flash Nonvolatile Functions - On-chip Real Time Clock w/ Alarm Interrupt - Battery backup support of 1 kB SRAM High-Speed Architecture - 4 clocks/machine cycle (8051 = 12) - Runs DC to 33 MHz clock rates - Single-cycle instruction in 121 ns - Dual data pointer - Optional variable length MOVX to access fast/slow RAM /peripherals Power Management Mode - Programmable clock source saves power - Runs from (crystal/64) or (crystal/1024) - Provides automatic hardware and software exit EMI Reduction Mode disables ALE Two full-duplex hardware serial ports High integration controller includes: - Power-Fail Reset - Early-Warning Power-Fail Interrupt - Programmable Watchdog Timer 14 total interrupt sources with 6 external
PACKAGE OUTLINE
7 8 1 47 46
DALLAS DS87C530 DS83C530
20 21 33 34
52-Pin PLCC 52-Pin CER QUAD 39 27
40
26
DALLAS DS87C530 DS83C530
52 14
1 13 52-Pin TQFP OUTLINE
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DS87C530/DS83C530
DESCRIPTION
The DS87C530/DS83C530 EPROM/ROM Micro with Real Time Clock is an 8051-compatible microcontroller based on the Dallas high-speed core. It uses 4 clocks per instruction cycle instead of 12 used by the standard 8051. It also provides a unique mix of peripherals not widely available on other processors. They include an on-chip Real Time Clock (RTC) and battery back up support for an on-chip 1k x 8 SRAM. The new Power Management Mode allows software to select reduced power operation while still processing. A combination of high performance microcontroller core, Real Time Clock, battery backed SRAM, and power management makes the DS87C530/DS83C530 ideal for instruments and portable applications. It also provides several peripherals found on other Dallas High-Speed Microcontrollers. These include two independent serial ports, two data pointers, on-chip power monitor with brown-out detection and a Watchdog Timer. Power Management Mode (PMM) allows software to select a slower CPU clock. While default operation uses four clocks per machine cycle, the PMM runs the processor at 64 or 1024 clocks per cycle. There is a corresponding drop in power consumption when the processor slows. The EMI reduction feature allows software to select a reduced emission mode. This disables the ALE signal when it is unneeded. The DS83C530 is a factory Mask ROM version of the DS87C530 designed for high-volume, costsensitive applications. It is identical in all respects to the DS87C530, except that the 16 kB of EPROM is replaced by a user-supplied application program. All references to features of the DS87C530 will apply to the DS83C530, with the exception of EPROM-specific features where noted. Please contact your local Dallas Semiconductor sales representative for ordering information. Note: The DS87C530/DS83C530 is a monolithic device. A user must supply an external battery or supercap and a 32.768 kHz timekeeping crystal to have permanently powered timekeeping or nonvolatile RAM. The DS87C530/DS83C530 provides all the support and switching circuitry needed to manage these resources.
ORDERING INFORMATION
PART NUMBER DS87C530-QCL DS87C530-QNL DS87C530-KCL DS87C530-ECL DS87C530-ENL DS83C530-QCL DS83C530-QNL DS83C530-ECL DS83C530-ENL PACKAGE 52-pin PLCC 52-pin PLCC 52-pin windowed CERQUAD 52-pin TQFP 52-pin TQFP 52-pin windowed CERQUAD 52-pin TQFP 52-pin TQFP 52-pin TQFP MAX. CLOCK SPEED 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz TEMPERATURE RANGE 0C to 70C -40C to +85C 0C to 70C 0C to 70C -40C to +85C 0C to 70C -40C to +85C 0C to 70C -40C to +85C
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DS87C530/DS83C530 BLOCK DIAGRAM Figure 1
PIN DESCRIPTION Table 1
PLCC 52 1, 25 29 26 12 TQFP 45 18, 46 22 19 5 SIGNAL NAME VCC GND VCC2 GND2 RST DESCRIPTION VCC - +5V. Processor power supply. GND - Processor digital circuit ground. VCC2 - +5V Real Time Clock supply. VCC2 is isolated from VCC to isolate the RTC from digital noise. GND2 - Real Time Clock circuit ground. RST - Input. This pin contains a Schmitt voltage input to recognize external active high Reset inputs. The pin also employs an internal pulldown resistor to allow for a combination of wired OR external Reset sources. An RC is not required for power-up, as the device provides this function internally. XTAL1, XTAL2 - The crystal oscillator pins provide support for parallel resonant, AT cut crystals. XTAL1 acts also as an input if there is an external clock source in place of a crystal. XTAL2 is the output of the crystal amplifier.
23 24
16 17
XTAL2 XTAL1
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PLCC 38
TQFP 31
SIGNAL NAME PSEN
PSEN
DESCRIPTION - Output. The Program Store Enable output. This signal is a chip enable for optional external ROM memory. PSEN will provide an active low pulse and is driven high when external ROM is not being accessed. ALE - Output. The Address Latch Enable output latches the external address LSB from the multiplexed address/data bus on Port 0. This signal is commonly connected to the latch enable of an external 373 family transparent latch. ALE has a pulse width of 1.5 XTAL1 cycles and a period of four XTAL1 cycles. ALE is forced high when the device is in a Reset condition. ALE can be disabled and forced high by writing ALEOFF=1 (PMR.2). ALE operates independently of ALEOFF during external memory accesses. Port 0 (AD0-7) - I/O. Port 0 is an open-drain, 8-bit bi-directional I/O port. As an alternate function Port 0 can function as the multiplexed address/data bus to access off-chip memory. During the time when ALE is high, the LSB of a memory address is presented. When ALE falls to a logic 0, the port transitions to a bidirectional data bus. This bus is used to read external ROM and read/ write external RAM memory or peripherals. When used as a memory bus, the port provides active high drivers. The reset condition of Port 0 is tri-state. Pullup resistors are required when using Port 0 as an I/O port. Port 1 - I/O. Port 1 functions as both an 8-bit bi-directional I/O port and an alternate functional interface for Timer 2 I/O, new External Interrupts, and new Serial Port 1. The reset condition of Port 1 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes the output high (and input) state. The alternate modes of Port 1 are outlined as follows. Port Alternate Function P1.0 T2 External I/O for Timer/Counter 2 P1.1 T2EX Timer/Counter 2 Capture/Reload Trigger P1.2 RXD1 Serial Port 1 Input P1.3 TXD1 Serial Port 1 Output P1.4 INT2 External Interrupt 2 (Positive Edge Detect) P1.5 INT3 External Interrupt 3 (Negative Edge Detect) P1.6 INT4 External Interrupt 4 (Positive Edge Detect) P1.7 INT5 External Interrupt 5 (Negative Edge Detect) 4 of 44
39
32
ALE
50 49 48 47 46 45 44 43
43 42 41 40 39 38 37 36
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7)
3-10
48-52, 1-3
P1.0 - P1.7
3 4 5 6 7 8 9 10
48 49 50 51 52 1 2 3
DS87C530/DS83C530
PLCC 30 31 32 33 34 35 36 37
TQFP 23 24 25 26 27 28 29 30
SIGNAL NAME P2.0 (AD8) P2.1 (AD9) P2.2 (AD10) P2.3 (AD11) P2.4 (AD12) P2.5 (AD13) P2.6 (AD14) P2.7 (AD15)
DESCRIPTION Port 2 (A8-15) - I/O. Port 2 is a bi-directional I/O port. The reset condition of Port 2 is logic high. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. As an alternate function Port 2 can function as MSB of the external address bus. This bus can be used to read external ROM and read/write external RAM memory or peripherals. Port 3 - I/O. Port 3 functions as both an 8-bit bi-directional I/O port and an alternate functional interface for external interrupts, Serial Port 0, Timer 0 and 1 Inputs, and RD and WR strobes. The reset condition of Port 3 is with all bits at a logic 1. In this state, a weak pullup holds the port high. This condition also serves as an input mode, since any external circuit that writes to the port will overcome the weak pullup. When software writes a 0 to any port pin, the device will activate a strong pulldown that remains on until either a 1 is written or a reset occurs. Writing a 1 after the port has been at 0 will cause a strong transition driver to turn on, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port again becomes both the output high and input state. The alternate modes of Port 3 are outlined below. Port Alternate Function P3.0 RXD0 Serial Port 0 Input P3.1 TXD0 Serial Port 0 Output External Interrupt 0 P3.2 INT0 P3.3 INT1 External Interrupt 1 P3.4 T0 Timer 0 External Input P3.5 T1 Timer 1 External Input P3.6 WR External Data Memory Write Strobe External Data Memory Read Strobe P3.7 RD EA - Input. Connect to ground to use an external ROM. Internal RAM is still accessible as determined by register settings. Connect to VCC to use internal ROM. VBAT - Input. Connect to the power source that maintains SRAM and RTC when VCC < VBAT. May be connected to a 3V lithium battery or a super-cap. Connect to GND if battery will not be used with device.
15-22
8-15
P3.0 - P3.7
15 16 17 18 19 20 21 22 42
8 9 10 11 12 13 14 15 35
EA
51
44
VBAT
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PLCC 27, 28
TQFP 20, 21
SIGNAL NAME RTCX2, RTCX1
DESCRIPTION RTCX2, RTCX1 - Timekeeping crystal. A 32.768 kHz crystal between these pins supplies the time-base for the Real Time Clock. The device supports both 6 pF and 12.5 pF load capacitance crystals as selected by an SFR bit described below. To prevent noise from affecting the RTC, the RTCX2 and RTCX1 pin should be guard-ringed with GND2. NC - Reserved. These pins should not be connected. They are reserved for use with future devices in the family.
2, 11, 13, 14, 40, 41
4, 6, 7, 33, 34, 47
NC
COMPATIBILITY
The DS87C530/DS83C530 is a fully static, CMOS 8051-compatible microcontroller designed for high performance. While remaining familiar to 8051 users, it has many new features. In general, software written for existing 8051-based systems works without modification on the DS87C530/DS83C530. The exception is critical timing since the High Speed Micro performs its instructions much faster than the original for any given crystal selection. The DS87C530/DS83C530 runs the standard 8051 instruction set. It is not pin-compatible with other 8051s due to the timekeeping crystal. The DS87C530/DS83C530 provides three 16-bit timer/counters, full-duplex serial port (2), 256 bytes of direct RAM plus 1 kB of extra MOVX RAM. I/O ports have the same operation as a standard 8051 product. Timers will default to a 12-clock per cycle operation to keep their timing compatible with original 8051 systems. However, timers are individually programmable to run at the new 4 clocks per cycle if desired. The PCA is not supported. The DS87C530/DS83C530 provides several new hardware features implemented by new Special Function Registers. A summary of these SFRs is provided below.
PERFORMANCE OVERVIEW
The DS87C530/DS83C530 features a high-speed, 8051-compatible core. Higher speed comes not just from increasing the clock frequency, but from a newer, more efficient design. This updated core does not have the dummy memory cycles that are present in a standard 8051. A conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS87C530/DS83C530, the same machine cycle takes 4 clocks. Thus the fastest instruction, one machine cycle, executes three times faster for the same crystal frequency. Note that these are identical instructions. The majority of instructions on the DS87C530/DS83C530 will see the full 3 to 1 speed improvement. Some instructions will get between 1.5 and 2.4 to 1 improvement. All instructions are faster than the original 8051. The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement of individual programs will depend on the actual instructions used. Speed-sensitive applications would make the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved opcodes makes dramatic speed improvements likely for any code. These architecture improvements produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer feature also allows the user to eliminate wasted instructions when moving blocks of memory. 6 of 44
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INSTRUCTION SET SUMMARY
All instructions perform the same functions as their 8051 counterparts. Their effect on bits, flags, and other status functions is identical. However, the timing of each instruction is different. This applies both in absolute and relative number of clocks. For absolute timing of real-time events, the timing of software loops can be calculated using a table in the High-Speed Microcontroller User's Guide. However, counter/timers default to run at the older 12 clocks per increment. In this way, timer-based events occur at the standard intervals with software executing at higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor operation. The relative time of two instructions might be different in the new architecture than it was previously. For example, in the original architecture, the "MOVX A, @DPTR" instruction and the "MOV direct, direct" instruction used two machine cycles or 24 oscillator cycles. Therefore, they required the same amount of time. In the DS87C530/DS83C530, the MOVX instruction takes as little as two machine cycles or eight oscillator cycles but the "MOV direct, direct" uses three machine cycles or 12 oscillator cycles. While both are faster than their original counterparts, they now have different execution times. This is because the DS87C530/DS83C530 usually uses one instruction cycle for each instruction byte. The user concerned with precise program timing should examine the timing of each instruction for familiarity with the changes. Note that a machine cycle now requires just 4 clocks, and provides one ALE pulse per cycle. Many instructions require only one cycle, but some require five. In the original architecture, all were one or two cycles except for MUL and DIV. Refer to the High-Speed Microcontroller User's Guide for details and individual instruction timing.
SPECIAL FUNCTION REGISTERS
Special Function Registers (SFRs) control most special features of the DS87C530/DS83C530. This allows the device to incorporate new features but remain instruction set compatible with the 8051. EQUATE statements can be used to define the new SFR to an assembler or compiler. All SFRs contained in the standard 80C52 are duplicated in this device. Table 2 shows the register addresses and bit locations. The High-Speed microcontroller User's Guide describes all SFRs.
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SPECIAL FUNCTION REGISTER LOCATIONS Table 2 * Functions not present in the 80C52 are in bold
REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
P0 SP DPL DPH
DPL1 DPH1 DPS
P0.7
P0.6
P0.5
P0.4
P0.3
P0.2
P0.1
P0.0
80h 81h 82h 83h 84h 85h
0
SMOD_0
0 SMOD0
0
0
0
0
0
SEL
86h 87h 88h 89h 8Ah 8Bh 8Ch 8Dh
PCON TCON TMOD TL0 TL1 TH0 TH1
CKCON
TF0 M1
TR0 M0
GF1 IE1 GATE
GF0 IT1 C/ T
STOP IE0 M1
IDLE IT0 M0
TF1 GATE
TR1 C/ T
WD1
WD0
T2M
T1M
T0M
MD2
MD1
MD0
8Eh 90h 91h 96h 98h 99h A0h A8h A9h AAh
P1
EXIF TRIM
P1.7
IE5 E4K
SM0/FE_0
P1.6
IE4 X12/ 6
P1.5
IE3 TRM2
P1.4
IE2
TRM2
P1.3
XT/RG TRM1
P1.2
RGMD
TRM1
P1.1
RGSL TRM0
P1.0
BGS
TRM0
SCON0 SBUF0 P2 IE SADDR0 SADDR1 P3 IP SADEN0 SADEN1
SCON1 SBUF1 ROMSIZE PMR STATUS
SM1_0 P2.6 ES1
SM2_0 P2.5 ET2
REN_0 P2.4 ES0
TB8_0 P2.3 ET1
RB8_0 P2.2 EX1
TI_0 P2.1 ET0
RI_0 P2.0 EX0
P2.7 EA
P3.7 -
P3.6 PS1
P3.5 PT2
P3.4 PS0
P3.3 PT1
P3.2 PX1
P3.1 PT0
P3.0 PX0
B0h B8h B9h BAh
SM0/FE_1
SM1_1 CD0 HIP
SM2_1 SWB LIP
REN_1 XTUP
TB8_1 XTOFF SPTA1
RB8_1 RMS2
ALEOFF
TI_1 RMS1 DME1 SPTA0
RI_1 RMS0 DME0 SPRA0
C0h C1h C2h C4h C5h C7h C8h C9h CAh CBh CCh CDh
CD1 PIP
SPRA1
TA T2CON T2MOD RCAP2L RCAP2H TL2 TH2 TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ T2 T2OE
CP/ RL2
DCEN
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REGISTER BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ADDRESS
PSW
WDCON
CY
SMOD_1
AC
POR -
F0
EPFI ERTCI
RS1
PFI EWDI
RS0
WDIP EX5
OV
WTRF EX4
FL
EWT EX3
P
RWT EX2
D0h D8h E0h E8h F0h F2h
ACC
EIE -
B
RTASS RTAS RTAM RTAH EIP RTCC RTCSS RTCS RTCM RTCH RTCD0 RTCD1
0 0 0
SSCE
0 0 0
SCE
F3h F4h 0
PRTCI MCE PWDI HCE PX5 RTCRE PX4 RTCWE PX3 RTCIF PX2 RTCE
F5h F8h F9h FAh FBh FCh FDh FEh FFh
0 0
0 0
NONVOLATILE FUNCTIONS
The DS87C530/DS83C530 provides two functions that are permanently powered if a user supplies an external energy source. These are an on-chip Real Time Clock and a nonvolatile SRAM. The chip contains all related functions and controls. The user must supply a backup source and a 32.768 kHz timekeeping crystal.
REAL TIME CLOCK
The on-chip Real Time Clock (RTC) keeps time of day and calendar functions. Its time base is a 32.768 kHz crystal between pins RTCX1 and RTCX2. The RTC maintains time to 1/256 of a second. It also allows a user to read (and write) seconds, minutes, hours, day of the week, and date. The clock organization is shown in Figure 2. Timekeeping registers allow easy access to commonly needed time values. For example, software can simply check the elapsed number of minutes by reading one register. Alternately, it can read the complete time of day, including subseconds, in only four registers. The calendar stores its data in binary form. While this requires software translation, it allows complete flexibility as to the exact value. A user can start the calendar with a variety of selections since it is simply a 16-bit binary number of days. This number allows a total range of 179 years beginning from 0000. The RTC features a programmable alarm condition. A user selects the alarm time. When the RTC reaches the selected value, it sets a flag. This will cause an interrupt if enabled, even in Stop mode. The alarm consists of a comparator that matches the user value against the RTC actual value. A user can select a match for 1 or more of the sub-seconds, seconds, minutes, or hours. This allows an interrupt automatically to occur once per second, once per minute, once per hour, or once per day. Enabling interrupts with no match will generate an interrupt 256 times per second. Software enables the timekeeper oscillator using the RTC Enable bit in the RTC Control register (F9h). This starts the clock. It can disable the oscillator to preserve the life of the backup energy-source if 9 of 44
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unneeded. Values in the RTC Control register are maintained by the backup source through power failure. Once enabled, the RTC maintains time for the life of the backup source even when VCC is removed. The RTC will maintain an accuracy of 2 minutes per month at 25C. Under no circumstances are negative voltages, of any amplitude, allowed on any pin while the device is in data retention mode (VCC < VBAT). Negative voltages will shorten battery life, possibly corrupting the contents of internal SRAM and the RTC.
REAL TIME CLOCK Figure 2
NONVOLATILE RAM
The 1k x 8 on-chip SRAM can be nonvolatile if an external backup energy source is used. This allows the device to log data or to store configuration settings. Internal switching circuits will detect the loss of VCC and switch SRAM power to the backup source on the VBAT pin. The 256 bytes of direct RAM are not affected by this circuit and are volatile.
CRYSTAL AND BACKUP SOURCES
To use the unique functions of the DS87C530/DS83C530, a 32.768 kHz timekeeping crystal and a backup energy source are needed. The following describes guidelines for choosing these devices.
Timekeeping Crystal
The DS87C530/DS83C530 can use a standard 32.768 kHz crystal as the RTC time base. There are two versions of standard crystals available, with 6 pF and 12.5 pF load capacitance. The tradeoff is that the 6 pF uses less power, giving longer life while VCC is off, but is more sensitive to noise and board layout. The 12.5 pF crystal uses more power, giving a shorter battery backed life, but produces a more robust oscillator. Bit 6 in the RTC Trim register (TRIM; 96h) must be programmed to specify the crystal type for the oscillator. When TRIM.6 = 1, the circuit expects a 12.5 pF crystal. When TRIM.6 = 0, it expects a 6 pF crystal. This bit will be nonvolatile so these choices will remain while the backup source is present. A guard ring (connected to the Real Time Clock ground) should encircle the RTCX1 and RTCX2 pins.
Backup Energy Source
The DS87C530/DS83C530 uses an external energy source to maintain timekeeping and SRAM data without VCC. This source can be either a battery or 0.47 F super cap and should be connected to the VBAT 10 of 44
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pin. The nominal battery voltage is 3V. The VBAT pin will not source current. Therefore, a super cap requires an external resistor and diode to supply charge. The backup lifetime is a function of the battery capacity and the data retention current drain. This drain is specified in the electrical specifications. The circuit loads the VBAT only when VCC has fallen below VBAT. Thus the actual lifetime depends not only on the current and battery capacity, but also on the portion of time without power. A very small lithium cell provides a lifetime of more than 10 years.
INTERNAL BACKUP CIRCUIT Figure 3
IMPORTANT APPLICATION NOTE
The pins on the DS87C530/DS83C530 are generally as resilient as other CMOS circuits. They have no unusual susceptibility to electrostatic discharge (ESD) or other electrical transients. However, no pin on the DS87C530/DS83C530 should ever be taken to a voltage below ground. Negative voltages on any pin can turn on internal parasitic diodes that draw current directly from the battery. If a device pin is connected to the "outside world" where it may be handled or come in contact with electrical noise, protection should be added to prevent the device pin from going below -0.3V. Some power supplies can give a small undershoot on power up, which should be prevented. Application Note 93, "Design Guidelines for Microcontrollers Incorporating NV RAM," discusses how to protect the DS87C530/DS83C530 against these conditions.
MEMORY RESOURCES
Like the 8051, the DS87C530/DS83C530 uses three memory areas. The total memory configuration of the device is 16kB of ROM, 1kB of data SRAM and 256 bytes of scratchpad or direct RAM. The 1kB of data space SRAM is read/write accessible and is memory mapped. This on-chip SRAM is reached by the MOVX instruction. It is not used for executable memory. The scratchpad area is 256 bytes of register mapped RAM and is identical to the RAM found on the 80C52. There is no conflict or overlap among the 256 bytes and the 1 kB as they use different addressing modes and separate instructions.
OPERATIONAL CONSIDERATION
The erasure window of the windowed CERQUAD should be covered without regard to the programmed/ unprogrammed state of the EPROM. Otherwise, the device may not meet the AC and DC parameters listed in the datasheet.
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PROGRAM MEMORY ACCESS
On-chip ROM begins at address 0000h and is contiguous through 3FFFh (16kB). Exceeding the maximum address of on-chip ROM will cause the DS87C530/DS83C530 to access off-chip memory. However, the maximum on-chip decoded address is selectable by software using the ROMSIZE feature. Software can cause the microcontroller to behave like a device with less on-chip memory. This is beneficial when overlapping external memory, such as Flash, is used. The maximum memory size is dynamically variable. Thus a portion of memory can be removed from the memory map to access off-chip memory, then restored to access on-chip memory. In fact, all of the onchip memory can be removed from the memory map allowing the full 64 kB memory space to be addressed from off-chip memory. ROM addresses that are larger than the selected maximum are automatically fetched from outside the part via Ports 0 and 2. A depiction of the ROM memory map is shown in Figure 4. The ROMSIZE register is used to select the maximum on-chip decoded address for ROM. Bits RMS2, RMS1, RMS0 have the following effect: RMS2 0 0 0 0 1 1 1 1 RMS1 0 0 1 1 0 0 1 1 RMS0 0 1 0 1 0 1 0 1 Maximum on-chip ROM Address 0 kB 1 kB 2 kB 4 kB 8 kB 16 kB (default) Invalid - reserved Invalid - reserved
The reset default condition is a maximum on-chip ROM address of 16 kB. Thus no action is required if this feature is not used. When accessing external program memory, the first 16 kB would be inaccessible. To select a smaller effective ROM size, software must alter bits RMS2-RMS0. Altering these bits requires a Timed Access procedure as explained below. Care should be taken so that changing the ROMSIZE register does not corrupt program execution. For example, assume that a device is executing instructions from internal program memory near the 12 kB boundary (~3000h) and that the ROMSIZE register is currently configured for a 16 kB internal program space. If software reconfigures the ROMSIZE register to 4 kB (0000h-0FFFh) in the current state, the device will immediately jump to external program execution because program code from 4kB to 16kB (1000h-3FFFh) is no longer located on-chip. This could result in code misalignment and execution of an invalid instruction. The recommended method is to modify the ROMSIZE register from a location in memory that will be internal (or external) both before and after the operation. In the above example, the instruction which modifies the ROMSIZE register should be located below the 4 kB (1000h) boundary, so that it will be unaffected by the memory modification. The same precaution should be applied if the internal program memory size is modified while executing from external program memory. Off-chip memory is accessed using the multiplexed address/data bus on P0 and the MSB address on P2. While serving as a memory bus, these pins are not I/O ports. This convention follows the standard 8051 12 of 44
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method of expanding on-chip memory. Off-chip ROM access also occurs if the EA pin is a logic 0. EA overrides all bit settings. The PSEN signal will go active (low) to serve as a chip enable or output enable when Ports 0 and 2 fetch from external ROM.
ROM MEMORY MAP Figure 4
DATA MEMORY ACCESS
Unlike many 8051 derivatives, the DS87C530/DS83C530 contains on-chip data memory. It also contains the standard 256 bytes of RAM accessed by direct instructions. These areas are separate. The MOVX instruction accesses the on-chip data memory. Although physically on-chip, software treats this area as though it was located off-chip. The 1 kB of SRAM is between address 0000h and 03FFh. Access to the on-chip data RAM is optional under software control. When enabled by software, the data SRAM is between 0000h and 03FFh. Any MOVX instruction that uses this area will go to the on-chip RAM while enabled. MOVX addresses greater than 03FFh automatically go to external memory through Ports 0 and 2. When disabled, the 1 kB memory area is transparent to the system memory map. Any MOVX directed to the space between 0000h and FFFFh goes to the expanded bus on Ports 0 and 2. This also is the default condition. This default allows the DS87C530/DS83C530 to drop into an existing system that uses these addresses for other hardware and still have full compatibility. The on-chip data area is software selectable using 2 bits in the Power Management Register at location C4h. This selection is dynamically programmable. Thus access to the on-chip area becomes transparent to reach off-chip devices at the same addresses. The control bits are DME1 (PMR.1) and DME0 (PMR.0). They have the following operation:
DATA MEMORY ACCESS CONTROL Table 3
DME1 0 0 1 1 DME0 0 1 0 1 DATA MEMORY ADDRESS 0000h - FFFFh 0000h - 03FFh 0400h - FFFFh Reserved 0000h - 03FFh 0400h - FFFBh FFFCh FFFDh - FFFh MEMORY FUNCTION External Data Memory * Default condition Internal SRAM Data Memory External Data Memory Reserved Internal SRAM Data Memory Reserved - no external access Read access to the status of lock bits Reserved - no external access
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Notes on the status byte read at FFFCh with DME1, 0 = 1, 1: Bits 2-0 reflect the programmed status of the security lock bits LB2-LB0. They are individually set to a logic 1 to correspond to a security lock bit that has been programmed. These status bits allow software to verify that the part has been locked before running if desired. The bits are read-only. Note: After internal MOVX SRAM has been initialized, changing bits DEM0/1 will have no affect on the contents of the SRAM.
STRETCH MEMORY CYCLE
The DS87C530/DS83C530 allows software to adjust the speed of off-chip data memory access. The microcontroller is capable of performing the MOVX in as few as two instruction cycles. The on-chip SRAM uses this speed and any MOVX instruction directed internally uses two cycles. However, the time can be stretched for interface to external devices. This allows access to both fast memory and slow memory or peripherals with no glue logic. Even in high-speed systems, it may not be necessary or desirable to perform off-chip data memory access at full speed. In addition, there are a variety of memory mapped peripherals such as LCDs or UARTs that are slow. The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below. It allows the user to select a Stretch value between 0 and 7. A Stretch of 0 will result in a two-machine cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically change this value depending on the particular memory or peripheral. On reset, the Stretch value will default to a 1, resulting in a three-cycle MOVX for any external access. Therefore, off-chip RAM access is not at full speed. This is a convenience to existing designs that may not have fast RAM in place. Internal SRAM access is always at full speed regardless of the Stretch setting. When desiring maximum speed, software should select a Stretch value of 0. When using very slow RAM or peripherals, select a larger Stretch value. Note that this affects data memory only and the only way to slow program memory (ROM) access is to use a slower crystal. Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all related timing. Also, setup and hold times are increased by 1 clock when using any Stretch greater than 0. This results in a wider read/write strobe and relaxed interface timing, allowing more time for memory/peripherals to respond. The timing of the variable speed MOVX is in the Electrical Specifications. Table 4 shows the resulting strobe widths for each Stretch value. The memory Stretch uses the Clock Control Special Function Register at SFR location 8Eh. The Stretch value is selected using bits CKCON.2-0. In the table, these bits are referred to as M2 through M0. The first Stretch (default) allows the use of common 120 ns RAMs without dramatically lengthening the memory access.
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DATA MEMORY CYCLE STRETCH VALUES Table 4
CKCON.2-0 M2 M1 M0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 MEMORY CYCLES 2 (forced internal) 3 (default external) 4 5 6 7 8 9 OR WR STROBE WIDTH IN CLOCKS 2 4 8 12 16 20 24 28
RD
STROBE WIDTH TIME @ 33 MHz 60 ns 121 ns 242 ns 364 ns 485 ns 606 ns 727 ns 848 ns
DUAL DATA POINTER
The timing of block moves of data memory is faster using the Dual Data Pointer (DPTR). The standard 8051 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the DS87C530/DS83C530, the standard data pointer is called DPTR, located at SFR addresses 82h and 83h. These are the standard locations. Using DPTR requires no modification of standard code. The new DPTR at SFR 84h and 85h is called DPTR1. The DPTR Select bit (DPS) chooses the active pointer. Its location is the lsb of the SFR location 86h. No other bits in register 86h have any effect and are 0. The user switches between data pointers by toggling the lsb of register 86h. The increment (INC) instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected DPTR for any activity. Therefore it takes only one instruction to switch from a source to a destination address. Using the Dual Data Pointer saves code from needing to save source and destination addresses when doing a block move. The software simply switches between DPTR and 1 once software loads them. The relevant register locations are as follows. DPL DPH DPL1 DPH1 DPS 82h 83h 84h 85h 86h Low byte original DPTR High byte original DPTR Low byte new DPTR High byte new DPTR DPTR Select (lsb)
POWER MANAGEMENT
Along with the standard Idle and power-down (Stop) modes of the standard 80C52, the DS87C530/DS83C530 provides a new Power Management Mode. This mode allows the processor to continue functioning, yet to save power compared with full operation. The DS87C530/DS83C530 also features several enhancements to Stop mode that make it more useful.
POWER MANAGEMENT MODE (PMM)
Power Management Mode offers a complete scheme of reduced internal clock speeds that allow the CPU to run software but to use substantially less power. During default operation, the DS87C530/DS83C530 uses four clocks per machine cycle. Thus the instruction cycle rate is (Clock/4). At 33 MHz crystal speed, the instruction cycle speed is 8.25 MHz (33/4). In PMM, the microcontroller continues to operate but uses an internally divided version of the clock source. This creates a lower power state without external components. It offers a choice of two reduced instruction cycle speeds (and two clock sources - discussed below). The speeds are (Clock/64) and (Clock/1024). 15 of 44
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Software is the only mechanism to invoke the PMM. Table 5 illustrates the instruction cycle rate in PMM for several common crystal frequencies. Since power consumption is a direct function of operating speed, PMM 1 eliminates most of the power consumption while still allowing a reasonable speed of processing. PMM 2 runs very slowly and provides the lowest power consumption without stopping the CPU. This is illustrated in Table 6. Note that PMM provides a lower power condition than Idle mode. This is because in Idle, all clocked functions such as timers run at a rate of crystal divided by 4. Since wake-up from PMM is as fast as or faster than from Idle and PMM allows the CPU to operate (even if doing NOPs), there is little reason to use Idle mode in new designs.
MACHINE CYCLE RATE Table 5
CRYSTAL SPEED 11.0592 MHz 16 MHz 25 MHz 33 MHz FULL OPERATION (4 CLOCKS) 2.765 MHz 4.00 MHz 6.25 MHz 8.25 MHz PMM1 (64 CLOCKS) 172.8 kHz 250.0 kHz 390.6 kHz 515.6 kHz PMM2 (1024 CLOCKS) 10.8 kHz 15.6 kHz 24.4 kHz 32.2 kHz
TYPICAL OPERATING CURRENT IN PMM Table 6
CRYSTAL SPEED 11.0592 MHz 16 MHz 25 MHz 33 MHz FULL OPERATION (4 CLOCKS) 13.1 mA 17.2 mA 25.7 mA 32.8 mA PMM1 (64 CLOCKS) 5.3 mA 6.4 mA 8.1 mA 9.8 mA PMM2 (1024 CLOCKS) 4.8 mA 5.6 mA 7.0 mA 8.2 mA
CRYSTALESS PMM
A major component of power consumption in PMM is the crystal amplifier circuit. The DS87C530/DS83C530 allows the user to switch CPU operation to an internal ring oscillator and turn off the crystal amplifier. The CPU would then have a clock source of approximately 2-4 MHz, divided by either 4, 64, or 1024. The ring is not accurate, so software cannot perform precision timing. However, this mode allows an additional saving of between 0.5 and 6.0 mA, depending on the actual crystal frequency. While this saving is of little use when running at 4 clocks per instruction cycle, it makes a major contribution when running in PMM1 or PMM2.
PMM OPERATION
Software invokes the PMM by setting the appropriate bits in the SFR area. The basic choices are divider speed and clock source. There are three speeds (4, 64, and 1024) and two clock sources (crystal, ring). Both the decisions and the controls are separate. Software will typically select the clock speed first. Then, it will perform the switch to ring operation if desired. Lastly, software can disable the crystal amplifier if desired. There are two ways of exiting PMM. Software can remove the condition by reversing the procedure that invoked PMM or hardware can (optionally) remove it. To resume operation at a divide by 4 rate under software control, simply select 4 clocks per cycle, then crystal based operation if relevant. When 16 of 44
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disabling the crystal as the time base in favor of the ring oscillator, there are timing restrictions associated with restarting the crystal operation. Details are described below. There are three registers containing bits that are concerned with PMM functions. They are Power Management Register (PMR; C4h), Status (STATUS; C5h), and External Interrupt Flag (EXIF; 91h)
Clock Divider
Software can select the instruction cycle rate by selecting bits CD1 (PMR.7) and CD0 (PMR.6) as follows: CD1 0 0 1 1 CD0 0 1 0 1 Cycle rate Reserved 4 clocks (default) 64 clocks 1024 clocks
The selection of instruction cycle rate will take effect after a delay of one instruction cycle. Note that the clock divider choice applies to all functions including timers. Since baud rates are altered, it will be difficult to conduct serial communication while in PMM. There are minor restrictions on accessing the clock selection bits. The processor must be running in a 4 clock state to select either 64 (PMM1) or 1024 (PMM2) clocks. This means software cannot go directly from PMM1 to PMM2 or visa versa. It must return to a 4-clock rate first.
Switchback
To return to a 4-clock rate from PMM, software can simply select the CD1 and CD0 clock control bits to the 4 clocks per cycle state. However, the DS87C530/DS83C530 provides several hardware alternatives for automatic Switchback. If Switchback is enabled, then the device will automatically return to a 4-clock per cycle speed when an interrupt occurs from an enabled, valid external interrupt source. A Switchback will also occur when a UART detects the beginning of a serial start bit if the serial receiver is enabled (REN=1). Note the beginning of a start bit does not generate an interrupt; this occurs on reception of a complete serial word. The automatic Switchback on detection of a start bit allows hardware to correct baud rates in time for a proper serial reception. A Switchback will also occur when a byte is written to the SBUF0 or SBUF1 for transmission. Switchback is enabled by setting the SWB bit (PMR.5) to a 1 in software. For an external interrupt, Switchback will occur only if the interrupt source could really generate the interrupt. For example, if INT0 is enabled but has a low priority setting, then Switchback will not occur on INT0 if the CPU is servicing a high priority interrupt.
Status
Information in the Status register assists decisions about switching into PMM. This register contains information about the level of active interrupts and the activity on the serial ports. The DS87C530/DS83C530 supports three levels of interrupt priority. These levels are Power-fail, High, and Low. Bits STATUS.7-5 indicate the service status of each level. If PIP (Power-fail Interrupt Priority; STATUS. 7) is a 1, then the processor is servicing this level. If either HIP (High Interrupt Priority; STATUS.6) or LIP (Low Interrupt Priority; STATUS.5) is high, then the corresponding level is in service.
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Software should not rely on a lower priority level interrupt source to remove PMM (Switchback) when a higher level is in service. Check the current priority service level before entering PMM. If the current service level locks out a desired Switchback source, then it would be advisable to wait until this condition clears before entering PMM. Alternately, software can prevent an undesired exit from PMM by entering a low priority interrupt service level before entering PMM. This will prevent other low priority interrupts from causing a Switchback. Status also contains information about the state of the serial ports. Serial Port Zero Receive Activity (SPRA0; STATUS.0) indicates a serial word is being received on Serial Port 0 when this bit is set to a 1. Serial Port 0 Transmit Activity (SPTA0; STATUS.1) indicates that the serial port is still shifting out a serial transmission. STATUS.2 and STATUS.3 provide the same information for Serial Port 1, respectively. These bits should be interrogated before entering PMM1 or PMM2 to ensure that no serial port operations are in progress. Changing the clock divisor rate during a serial transmission or reception will corrupt the operation.
Crystal/Ring Operation
The DS87C530/DS83C530 allows software to choose the clock source as an independent selection from the instruction cycle rate. The user can select crystal-based or ring oscillator-based operation under software control. Power-on reset default is the crystal (or external clock) source. The ring may save power depending on the actual crystal speed. To save still more power, software can then disable the crystal amplifier. This process requires two steps. Reversing the process also requires two steps. The XT/ RG bit (EXIF.3) selects the crystal or ring as the clock source. Setting XT/ RG = 1 selects the crystal. Setting XT/ RG = 0 selects the ring. The RGMD (EXIF.2) bit serves as a status bit by indicating the active clock source. RGMD = 0 indicates the CPU is running from the crystal. RGMD = 1 indicates it is running from the ring. When operating from the ring, disable the crystal amplifier by setting the XTOFF bit (PMR.3) to a 1. This can only be done when XT/ RG = 0. When changing the clock source, the selection will take effect after a one instruction cycle delay. This applies to changes from crystal to ring and vise versa. However, this assumes that the crystal amplifier is running. In most cases, when the ring is active, software previously disabled the crystal to save power. If ring operation is being used and the system must switch to crystal operation, the crystal must first be enabled. Set the XTOFF bit to a 0. At this time, the crystal oscillation will begin. The DS87C530/DS83C530 then provides a warm-up delay to make certain that the frequency is stable. Hardware will set the XTUP bit (STATUS.4) to a 1 when the crystal is ready for use. Then software should write XT/ RG to a 1 to begin operating from the crystal. Hardware prevents writing XT/ RG to a 1 before XTUP = 1. The delay between XTOFF = 0 and XTUP = 1 will be 65,536 crystal clocks in addition to the crystal cycle startup time. Switchback has no effect on the clock source. If software selects a reduced clock divider and enables the ring, a Switchback will only restore the divider speed. The ring will remain as the time base until altered by software. If there is serial activity, Switchback usually occurs with enough time to create proper baud rates. This is not true if the crystal is off and the CPU is running from the ring. If sending a serial character that wakes the system from crystal-less PMM, then it should be a dummy character of no importance with a subsequent delay for crystal startup. The following table is a summary of the bits relating to PMM and its operation. The flow chart below illustrates a typical decision set associated with PMM. 18 of 44
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PMM CONTROL AND STATUS BIT SUMMARY Table 7
BIT NAME XT/ RG LOCATION EXIF.3 FUNCTION Control. XT/ RG =1, runs from crystal or external clock; XT/ RG =0, runs from internal ring oscillator. Status. RGMD=1, CPU clock = ring; RGMD=0, CPU clock = crystal. Control. CD1,0=01, 4 clocks; CS1,0=10, PMM1; CD1,0=11, PMM2. Control. SWB=1, hardware invokes switchback to 4 clocks, SWB=0, no hardware switchback. Control. Disables crystal operation after ring is selected. Status. 1 indicates a power-fail interrupt in service. Status. 1 indicates high priority interrupt in service. Status. 1 indicates low priority interrupt in service. Status. 1 indicates that the crystal has stabilized. Status. Serial transmission on serial port 1. Status. Serial word reception on serial port 1. Status. Serial transmission on serial port 0. Status. Serial word reception on serial port 0. RESET X WRITE ACCESS 0 to 1 only when XTUP=1 and XTOFF=0 None Write CD1,0=10 or 11 only from CD1,0=01 Unrestricted 0 0 0 0 1 0 0 0 0 1 only when XT/ RG =0 None None None None None None None None
RGMD CD1, CD0
EXIF.2 PMR7, PMR.6 PMR.5
0 0, 1
SWB
0
XTOFF PIP HIP LIP XTUP SPTA1 SPRA1 SPTA0 SPRA0
PMR.3 STATUS.7 STATUS.6 STATUS.5 STATUS.4 STATUS.3 STATUS.2 STATUS.1 STATUS.0
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INVOKING AND CLEARING PMM Figure 3
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IDLE MODE
Setting the lsb of the Power Control register (PCON; 87h) invokes the Idle mode. Idle will leave internal clocks, serial ports and timers running. Power consumption drops because the CPU is not active. Since clocks are running, the Idle power consumption is a function of crystal frequency. It should be approximately 1/2 of the operational power at a given frequency. The CPU can exit the Idle state with any interrupt or a reset. Idle is available for backward software compatibility. The system can now reduce power consumption to below Idle levels by using PMM1 or PMM2 and running NOPs.
STOP MODE ENHANCEMENTS
Setting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest power state since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 A but is specified in the Electrical Specifications. The CPU will exit Stop mode from an external interrupt or a reset condition. Internally generated interrupts (timer, serial port, watchdog) are not useful since they require clocking activity. One exception is that a Real Time Clock interrupt can cause the device to exit Stop mode. This provides a very power efficient way of performing infrequent yet periodic tasks. The DS87C530/DS83C530 provides two enhancements to the Stop mode. As documented below, the device provides a band-gap reference to determine Power-fail Interrupt and Reset thresholds. The default state is that the band-gap reference is off while in Stop mode. This allows the extremely low-power state mentioned above. A user can optionally choose to have the band-gap enabled during Stop mode. With the band-gap reference enabled, PFI and Power-fail Reset are functional and are a valid means for leaving Stop mode. This allows software to detect and compensate for a brown-out or power supply sag, even when in Stop mode. In Stop mode with the band-gap enabled, ICC will be approximately 50 A compared with 1 A with the band-gap off. If a user does not require a Power-fail Reset or Interrupt while in Stop mode, the band-gap can remain disabled. Only the most power sensitive applications should turn off the band-gap, as this results in an uncontrolled power-down condition. The control of the band-gap reference is located in the Extended Interrupt Flag register (EXIF; 91h). Setting BGS (EXIF.0) to a 1 will keep the band-gap reference enabled during Stop mode. The default or reset condition is with the bit at a logic 0. This results in the band-gap being off during Stop mode. Note that this bit has no control of the reference during full power, PMM, or Idle modes. The second feature allows an additional power saving option while also making Stop easier to use. This is the ability to start instantly when exiting Stop mode. It is the internal ring oscillator that provides this feature. This ring can be a clock source when exiting Stop mode in response to an interrupt. The benefit of the ring oscillator is as follows. Using Stop mode turns off the crystal oscillator and all internal clocks to save power. This requires that the oscillator be restarted when exiting Stop mode. Actual startup time is crystal-dependent, but is normally at least 4 ms. A common recommendation is 10 ms. In an application that will wake up, perform a short operation, then return to sleep, the crystal startup can be longer than the real transaction. However, the ring oscillator will start instantly. Running from the ring, the user can perform a simple operation and return to sleep before the crystal has even started. If a user selects the ring to provide the startup clock and the processor remains running, hardware will automatically switch to the crystal once a power-on reset interval (65536 clocks) has expired. Hardware uses this value to assure proper crystal start even though power is not being cycled.
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The ring oscillator runs at approximately 2-4 MHz but will not be a precise value. Do not conduct realtime precision operations (including serial communication) during this ring period. Figure 4 shows how the operation would compare when using the ring, and when starting up normally. The default state is to exit Stop mode without using the ring oscillator. The RGSL - Ring Select bit at EXIF.1 (EXIF; 91h) controls this function. When RGSL = 1, the CPU will use the ring oscillator to exit Stop mode quickly. As mentioned above, the processor will automatically switch from the ring to the crystal after a delay of 65,536 crystal clocks. For a 3.57 MHz crystal, this is approximately 18 ms. The processor sets a flag called RGMD- Ring Mode, located at EXIF.2, that tells software that the ring is being used. The bit will be a logic 1 when the ring is in use. Attempt no serial communication or precision timing while this bit is set, since the operating frequency is not precise.
RING OSCILLATOR EXIT FROM STOP MODE Figure 4
Note: Diagram assumes that the operation following Stop requires less than 18 ms to complete.
EMI REDUCTION
One of the major contributors to radiated noise in an 8051 based system is the toggling of ALE. The DS87C530/DS83C530 allows software to disable ALE when not used by setting the ALEOFF (PMR.2) bit to a 1. When ALEOFF = 1, ALE will still toggle during an off-chip MOVX. However, ALE will remain in a static when performing on-chip memory access. The default state of ALEOFF = 0 so ALE toggles with every instruction cycle.
PERIPHERAL OVERVIEW
The DS87C530/DS83C530 provides several of the most commonly needed peripheral functions in microcomputer-based systems. These new functions include a second serial port, Power-fail Reset, Power-fail Interrupt, and a programmable Watchdog Timer. These are described below, and more details are available in the High-Speed Microcontroller User's Guide.
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SERIAL PORTS
The DS87C530/DS83C530 provides a serial port (UART) that is identical to the 80C52. In addition it includes a second hardware serial port that is a full duplicate of the standard one. This port optionally uses pins P1.2 (RXD1) and P1.3 (TXD1). It has duplicate control functions included in new SFR locations. Both ports can operate simultaneously but can be at different baud rates or even in different modes. The second serial port has similar control registers (SCON1; C0h, SBUF1; C1h) to the original. The new serial port can only use Timer 1 for timer-generated baud rates.
TIMER RATE CONTROL
There is one important difference between the DS87C530/DS83C530 and 8051 regarding timers. The original 8051 used 12 clocks per cycle for timers as well as for machine cycles. The DS87C530/DS83C530 architecture normally uses 4 clocks per machine cycle. However, in the area of timers and serial ports, the DS87C530/DS83C530 will default to 12 clocks per cycle on reset. This allows existing code with real-time dependencies such as baud rates to operate properly. If an application needs higher speed timers or serial baud rates, the user can select individual timers to run at the 4-clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the relevant CKCON bit is a logic 1, the DS87C530/DS83C530 uses 4 clocks per cycle to generate timer speeds. When the bit is a 0, the DS87C530 uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5 selects the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Unless a user desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent.
POWER-FAIL RESET
The DS87C530/DS83C530 uses a precision band-gap voltage reference to decide if VCC is out of tolerance. While powering up, the internal monitor circuit maintains a reset state until VCC rises above the VRST level. Once above this level, the monitor enables the crystal oscillator and counts 65536 clocks. It then exits the reset state. This power-on reset (POR) interval allows time for the oscillator to stabilize. A system needs no external components to generate a power-related reset. Anytime VCC drops below VRST, as in power failure or a power drop, the monitor will generate and hold a reset. It occurs automatically, needing no action from the software. Refer to the Electrical Specifications for the exact value of VRST.
POWER-FAIL INTERRUPT
The voltage reference that sets a precise reset threshold also generates an optional early warning Powerfail Interrupt (PFI). When enabled by software, the processor will vector to program memory address 0033h if VCC drops below VPFW. PFI has the highest priority. The PFI enable is in the Watchdog Control SFR (WDCON - D8h). Setting WDCON.5 to a logic 1 will enable the PFI. Application software can also read the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt enable and software must manually clear it. If the PFI is enabled and the band-gap select bit (BGS) is set, a PFI will bring the device out of Stop mode.
WATCHDOG TIMER
To prevent software from losing control, the DS87C530/DS83C530 includes a programmable Watchdog Timer. The Watchdog is a free running timer that sets a flag if allowed to reach a preselected time-out. It can be (re)started by software. 23 of 44
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A typical application is to select the flag as a reset source. When the Watchdog times out it sets its flag, which generates reset. Software must restart the timer before it reaches its time-out or the processor is reset. Software can select one of four time-out values. Then, it restarts the timer and enables the reset function. After enabling the reset function, software must then restart the timer before its expiration or hardware will reset the CPU. Both the Watchdog Reset Enable and the Watchdog Restart control bits are protected by a "Timed Access" circuit. This prevents errant software from accidentally clearing the Watchdog. Time-out values are precise since they are a function of the crystal frequency as shown in Table 8. For reference, the time periods at 33 MHz also are shown. The Watchdog also provides a useful option for systems that do not require a reset circuit. It will set an interrupt flag 512 clocks before setting the reset flag. Software can optionally enable this interrupt source. The interrupt is independent of the reset. A common use of the interrupt is during debug, to show developers where the Watchdog times out. This indicates where the Watchdog must be restarted by software. The interrupt also can serve as a convenient time-base generator or can wake-up the processor from power saving modes. The Watchdog function is controlled by the Clock Control (CKCON - 8Eh), Watchdog Control (WDCON - D8h), and Extended Interrupt Enable (EIE - E8h) SFRs. CKCON.7 and CKCON.6 are WD1 and WD0 respectively and they select the Watchdog time-out period as shown in Table 8.
WATCHDOG TIME-OUT VALUES Table 8
WD1 0 0 1 1 WD0 0 1 0 1 INTERRUPT TIME-OUT 217 clocks 2 clocks 2 clocks 2 clocks
26 23 20
TIME (33 MHz) 3.9718 ms 31.77 ms 254.20 ms 2033.60 ms
RESET TIME-OUT 17 2 + 512 clocks 2 + 512 clocks 2 + 512 clocks 2 + 512 clocks
26 23 20
TIME (33 MHz) 3.9874 ms 31.79 ms 254.21 ms 2033.62 ms
As shown above, the Watchdog Timer uses the crystal frequency as a time base. A user selects one of four counter values to determine the time-out. These clock counter lengths are 217 = 131,072 clocks; 220 = 1,048,576; 223 = 8,388,608 clocks; and 226 = 67,108,864 clocks. The times shown in Table 8 above are with a 33 MHz crystal frequency. Once the counter chain has completed a full interrupt count, hardware will set an interrupt flag. Regardless of whether the user enables this interrupt, there are then 512 clocks left until the reset flag is set. Software can enable the interrupt and reset individually. Note that the Watchdog is a free running timer and does not require an enable. There are 5 control bits in special function registers that affect the Watchdog Timer and two status flags that report to the user. WDIF (WDCON.3) is the interrupt flag that is set at timer termination when there are 512 clocks remaining until the reset flag is set. WTRF (WDCON.2) is the flag that is set when the timer has completely timed out. This flag is normally associated with a CPU reset and allows software to determine the reset source. EWT (WDCON.1) is the enable for the Watchdog Timer reset function. RWT (WDCON.0) is the bit that software uses to restart the Watchdog Timer. Setting this bit restarts the timer for another full interval. Application software must set this bit before the time-out. Both of these bits are protected by Timed Access discussed below. As mentioned previously, WD1 and 0 (CKCON .7 and 6) select the time-out. The Reset Watchdog Timer bit (WDCON.0) should be asserted prior to modifying the Watchdog Timer Mode Select bits (WD1, WD0) to avoid corruption of the watchdog count. Finally, the 24 of 44
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user can enable the Watchdog Interrupt using EWDI (EIE.4). The Special Function Register map is shown above.
INTERRUPTS
The DS87C530/DS83C530 provides 14 interrupt sources with three priority levels. The Power-Fail Interrupt (PFI) has the highest priority. Software can assign high or low priority to other sources. All interrupts that are new to the 8051 family, except for the PFI, have a lower natural priority than the originals.
INTERRUPT SOURCES AND PRIORITIES Table 9
NAME PFI
INT0
DESCRIPTION Power Fail Interrupt External Interrupt 0 Timer 0 External Interrupt 1 Timer 1 TI0 or RI0 from serial port 0 Timer 2 TI1 or RI1 from serial port 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 Watchdog Time-Out Interrupt Real Time Clock Interrupt
VECTOR 33h 03h 0Bh 13h 1Bh 23h 2Bh 3Bh 43h 4Bh 53h 5Bh 63h 6Bh
NATURAL PRIORITY 1 2 3 4 5 6 7 8 9 10 11 12 13 14
8051/DALLAS DALLAS 8051 8051 8051 8051 8051 8051 DALLAS DALLAS DALLAS DALLAS DALLAS DALLAS DALLAS
TF0
INT1
TF1 SCON0 TF2 SCON1 INT2
INT3
INT4
INT5
WDTI RTCI
TIMED ACCESS PROTECTION
It is useful to protect certain SFR bits from an accidental write operation. The Timed Access procedure stops an errant CPU from accidentally changing these bits. It requires that the following instructions precede a write of a protected bit. MOV MOV 0C7h, #0AAh 0C7h, #55h
Writing an AAh then a 55h to the Timed Access register (location C7h) opens a three-cycle window for write access. The window allows software to modify a protected bit(s). If these instructions do not immediately precede the write operation, then the write will not take effect. The protected bits are:
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EXIF.0 WDCON.6 WDCON.1 WDCON.0 WDCON.3 ROMSIZE.2 ROMSIZE.1 ROMSIZE.0 TRIM.7-0 RTCC.2 RTCC.0
BGS POR EWT RWT WDIF RMS2 RMS1 RMS0 RTCWE RTCE
Band-gap Select Power-on Reset flag Enable Watchdog Reset Restart Watchdog Watchdog Interrupt Flag ROM size select 2 ROM size select 1 ROM size select 0 All RTC trim functions RTC Write Enable RTC Oscillator Enable
EPROM PROGRAMMING
The DS87C530 follows standards for a 16-kbyte EPROM version in the 8051 family. It is available in a UV erasable, ceramic windowed package and in plastic packages for one-time user-programmable versions. The part has unique signature information so programmers can support its specific EPROM options.
PROGRAMMING PROCEDURE
The DS87C530 should run from a clock speed between 4 and 6 MHz when programmed. The programming fixture should apply address information for each byte to the address lines and the data value to the data lines. The control signals must be manipulated as shown in Table 10. The diagram in Figure 5 shows the expected electrical connection for programming. Note that the programmer must apply addresses in demultiplexed fashion to Ports 1 and 2 with data on Port 0. Waveforms and timing are provided in the Electrical Specifications. Program the DS87C530 as follows: 1. Apply the address value, 2. Apply the data value, 3. Select the programming option from Table 10 using the control signals, 4. Increase the voltage on VPP from 5V to 12.75V if writing to the EPROM, 5. Pulse the PROG signal five times for EPROM array and 25 times for encryption table, lock bits, and other EPROM bits, 6. Repeat as many times as necessary.
SECURITY OPTIONS
The DS87C530 employs a standard three-level lock that restricts viewing of the EPROM contents. A 64byte Encryption Array allows the authorized user to verify memory by presenting the data in encrypted form.
Lock Bits
The security lock consists of 3 lock bits. These bits select a total of 4 levels of security. Higher levels provide increasing security but also limit application flexibility. Table 11 shows the security settings. Note that the programmer cannot directly read the state of the security lock. User software has access to this information as described in the Memory section.
Encryption Array
The Encryption Array allows an authorized user to verify EPROM without allowing the true memory to be dumped. During a verify, each byte is Exclusive NORed (XNOR) with a byte in the Encryption Array. 26 of 44
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This results in a true representation of the EPROM while the Encryption is unprogrammed (FFh). Once the Encryption Array is programmed in a non-FFh state, the verify value will be encrypted. For encryption to be effective, the Encryption Array must be unknown to the party that is trying to verify memory. The entire EPROM also should be a non-FFh state or the Encryption Array can be discovered. The Encryption Array is programmed as shown in Table 10. Note that the programmer can not read the array. Also note that the verify operation always uses the Encryption Array. The array has no impact while FFh. Simply programming the array to a non-FFh state will cause the encryption to function.
OTHER EPROM OPTIONS
The DS87C530 has user selectable options that must be set before beginning software execution. These options use EPROM bits rather than SFRs. Program the EPROM selectable options as shown in Table 10. The Option Register sets or reads these selections. The bits in the Option Control Register have the following function: Bit 7 -4 Reserved, program to a 1. Bit 3 Watchdog POR default. Set=1; Watchdog reset function is disabled on power-up. Set=0; Watchdog reset function is enabled automatically. Bit 2-0 Reserved. Program to a 1.
SIGNATURE
The Signature bytes identify the product and programming revision to EPROM programmers. This information is at programming addresses 30h, 31h, and 60h. This information is as follows:: Address 30h 31h 60h Value DAh 30h 01h Meaning Manufacturer Model Extension
EPROM PROGRAMMING MODES Table 10
MODE Program Code Data Verify Code Data Program Encryption Array Address 0-3Fh Program Lock Bits LB1 LB2 LB3 Program Option Register Address FCh RST H H H H H H H
PSEN
ALE/ PROG PL H PL PL PL PL PL H
EA/VPP 12.75V H 12.75V 12.75V 12.75V 12.75V 12.75V H
P2.6 L L L H H H L L
P2.7 H L H H H L H L
P3.3 H L H H H H H L
P3.6 H H L H L H L L
P3.7 H H H H L L L L
L L L L L L L
Read Signature or H L Option Registers 30, 31, 60, FCh * PL indicates pulse to a logic low.
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EPROM LOCK BITS Table 11
LEVEL 1 2 LOCK BITS LB1 LB2 LB3 U P U U U U PROTECTION No program lock. Encrypted verify if encryption table was programmed. Prevent MOVC instructions in external memory from reading program bytes in internal memory. EA is sampled and latched on reset. Allow no further programming of EPROM. Level 2 plus no verify operation. Also, prevent MOVX instructions in external memory from reading SRAM (MOVX) in internal memory. Level 3 plus no external execution.
3
P
P
U
4
P
P
P
EPROM PROGRAMMING CONFIGURATION Figure 5
ROM-SPECIFIC FEATURES
The DS83C530 supports a subset of the EPROM features found on the DS87C530.
SECURITY OPTIONS Lock Bits
The DS83C530 employs a lock that restricts viewing of the ROM contents. When set, the lock will prevent MOVC instructions in external memory from reading program bytes in internal memory. When locked, the EA pin is sampled and latched on reset. The lock setting is enabled or disabled when the devices are manufactured according to customer specifications. The lock bit cannot be read in software, and its status can only be determined by observing the operation of the device.
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Encryption Array
The DS83C530 Encryption Array allows an authorized user to verify ROM without allowing the true memory contents to be dumped. During a verify, each byte is Exclusive NORed (XNOR) with a byte in the Encryption Array. This results in a true representation of the ROM while the Encryption is unprogrammed (FFh). Once the Encryption Array is programmed in a non-FFh state, the Encryption Array is programmed (or optionally left unprogrammed) when the devices are manufactured according to customer specifications.
DS83C530 ROM VERIFICATION
The DS83C530 memory contents can be verified using a standard EPROM programmer. The memory address to be verified is placed on the pins shown in Figure 5, and the programming control pins are set to the levels shown in Table 10. The data at that location is then asserted on port 0.
DS83C530 SIGNATURE
The Signature bytes identify the DS83C530 to EPROM programmers. This information is at programming addresses 30h, 31h, and 60h. Because Mask ROM devices are not programmed in device programmers, most designers will find little use for the feature, and it is included only for compatibility. Address 30h 31h 60h Value DAh 31h 01h Meaning Manufacturer Model Extension
ABSOLUTE MAXIMUM RATINGS*
Voltage on Any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * -0.3V to +7.0V 0C to 70C -55C to +125C 260C for 10 seconds
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect reliability.
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DC ELECTRICAL CHARACTERISTICS
PARAMETER Supply Voltage Power-fail Warning Minimum Operating Voltage Backup Battery Voltage Supply Current Active Mode @ 33 MHz Supply Current Idle Mode @ 33 MHz Supply Current Stop Mode, Band-gap Disabled Supply Current Stop Mode, Band-gap Enabled Backup Supply Current, Data Retention Mode Input Low Level Input High Level Input High Level XTAL1 and RST Output Low Voltage @ IOL=1.6 mA Output Low Voltage Ports 0, 2, ALE , and PSEN @ IOL=3.2 mA Output High Voltage Ports 1, 2, 3, ALE, PSEN @ IOH=-50 A Output High Voltage Ports 1, 2, 3 @ IOH=-1.5 mA Output High Voltage Port 0 in Bus Mode IOH=-8 mA Input Low Current Ports 1, 2, 3 @ 0.45V Transition Current from 1 to 0 Ports 1, 2, 3 @ 2V Input Leakage Port 0, EA , pins, I/O Mode Input Leakage Port 0, Bus Mode RST Pull-down Resistance SYMBOL VCC VPFW VRST VBAT ICC IIdle IStop ISPBG IBAT VIL VIH VIH2 VOL1 VOL2 VOH1 VOH2 VOH3 IIL ITL IL IL RRST -10 -300 50 2.4 2.4 2.4 -55 -650 +10 +300 200 0 -0.3 2.0 3.5 0.15 0.15 MIN 4.5 4.25 4.0 2.5 TYP 5.0 4.38 4.13 3.0 30 15 1 50 0.5 +0.8 VCC+0.3 VCC+0.3 0.45 0.45 MAX 5.5 4.5 4.25 VCC-0.7 UNITS V V V V mA mA A A A V V V V V V V V A A A A k 2 3 4 4 11 1 1 1 1 1 1, 6 1, 7 1, 5 12 8 10 9 NOTES 1 1 1
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NOTES FOR DC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature operation unless otherwise noted. 1. All voltages are referenced to ground. 2. Active current measured with 33 MHz clock source on XTAL1, VCC=RST=5.5V, other pins disconnected. 3. Idle mode current measured with 33 MHz clock source on XTAL1, VCC=5.5V, RST at ground, other pins disconnected. 4. Stop mode current measured with XTAL1 and RST grounded, VCC=5.5V, all other pins disconnected. This value is not guaranteed. Users that are sensitive to this specification should contact Dallas Semiconductor for more information. 5. When addressing external memory. 6. RST=VCC. This condition mimics operation of pins in I/O mode. Port 0 is tristated in reset and when at a logic high state during I/O mode. 7. During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement reflects port in transition mode. 8. Ports 1, 2, and 3 source transition current when being pulled down externally. It reaches its maximum at approximately 2V. 9. 0.45TYPICAL ICC VERSUS FREQUENCY Figure 6
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AC ELECTRICAL CHARACTERISTICS
33 MHz PARAMETER Oscillator Freq. (Ext. Osc.) (Ext. Crystal) ALE Pulse Width Port 0 Address Valid to ALE Low Address Hold after ALE Low ALE low to Valid Instruction In ALE Low to PSEN Low
PSEN PSEN
VARIABLE CLOCK MIN 0 1 1.5tCLCL-5 0.5tCLCL-5 0.5tCLCL-5 MAX 33 33 UNITS MHz ns ns ns 2.5tCLCL-20 0.5tCLCL-5 2tCLCL-5 ns ns ns 2tCLCL-20 0 tCLCL-5 3tCLCL-20 3.5tCLCL-25 0 ns ns ns ns ns ns
SYMBOL 1/tCLCL tLHLL tAVLL tLLAX1 tLLIV tLLPL tPLPH tPLIV tPXIX tPXIZ tAVIV tAVIV2 tPLAZ
MIN 0 1 40 10 10
MAX 33 33
56 10 55 41 0 26 71 81 0
Pulse Width Low to Valid Instr. In
Input Instruction Hold after PSEN Input Instruction Float after PSEN Port 0 Address to Valid Instr. In Port 2 Address to Valid Instr. In
PSEN
Low to Address Float
NOTES FOR AC ELECTRICAL CHARACTERISTICS:
All parameters apply to both commercial and industrial temperature range operation unless otherwise noted. All signals rated over operating temperature. All signals characterized with load capacitance of 80 pF except Port 0, ALE, PSEN , RD and WR with 100 pF. Interfacing to memory devices with float times (turn off times) over 25 ns may cause contention. This will not damage the parts, but will cause an increase in operating current. Specifications assume a 50% duty cycle for the oscillator. Port 2 and ALE timing will change in relation to duty cycle variation.
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MOVX CHARACTERISTICS USING STRETCH MEMORY CYCLES
VARIABLE CLOCK PARAMETER Data Access ALE Pulse Width Address Hold after ALE Low for MOVX Write
RD
SYMBOL tLHLL2 tLLAX2 tRLRH tWLWH tRLDV tRHDX tRHDZ tLLDV tAVDV1 tAVDV2 tLLWL tAVWL1 tAVWL2 tQVWX tWHQX tRLAZ tWHLH
MIN 1.5tCLCL-5 2tCLCL-5 0.5tCLCL-5 tCLCL-5 2tCLCL-5 tMCS-10 2tCLCL-5 tMCS-10
MAX
UNITS ns ns ns ns
STRETCH tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0 tMCS=0 tMCS>0
Pulse Width Pulse Width Low Valid Data In
WR
RD
2tCLCL-20 tMCS-20 0 tCLCL-5 2tCLCL-5 2.5tCLCL-20
tMCS+tCLCL-40
ns ns ns ns ns ns ns ns ns ns ns
Data Hold after Read Data Float after Read ALE Low to Valid Data In Port 0 Address to Valid Data In Port 2 Address to Valid Data In ALE Low to RD or WR Low Port 0 Address to RD or WR Low Port 2 Address to RD or WR Low Data Valid to WR Transition Data Hold after Write
RD RD
3tCLCL-20
tMCS+1.5tCLCL-20
3.5tCLCL-20
tMCS+2tCLCL-20
0.5tCLCL-5 tCLCL-5 tCLCL-5 2tCLCL-5 1.5tCLCL-10 2.5tCLCL-10 -5 tCLCL-5 2tCLCL-5
0.5tCLCL+5 tCLCL+5
Low to Address Float or WR High to ALE High
-0.5tCLCL-5 0
ns
10 ns tMCS=0 tCLCL-5 tCLCL+5 tMCS>0 NOTE: tMCS is a time period related to the Stretch memory cycle selection. The following table shows the value of tMCS for each Stretch selection.
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M2 0 0 0 0 1 1 1 1
M1 0 0 1 1 0 0 1 1
M0 0 1 0 1 0 1 0 1
MOVX CYCLES 2 machine cycles 3 machine cycles (default) 4 machine cycles 5 machine cycles 6 machine cycles 7 machine cycles 8 machine cycles 9 machine cycles
tMCS 0 4 tCLCL 8 tCLCL 12 tCLCL 16 tCLCL 20 tCLCL 24 tCLCL 28 tCLCL
EXTERNAL CLOCK CHARACTERISTICS
PARAMETER Clock High Time Clock Low Time Clock Rise Time Clock Fall Time SYMBOL tCHCX tCLCX tCLCL tCHCL MIN 10 10 5 5 TYP MAX UNITS ns ns ns ns NOTES
SERIAL PORT MODE 0 TIMING CHARACTERISTICS
PARAMETER Serial Port Clock Cycle Time SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Output Data Setup to Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Output Data Hold from Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Input Data Hold after Clock Rising SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle Clock Rising Edge to Input Data Valid SM2=0, 12 clocks per cycle SM2=1, 4 clocks per cycle SYMBOL tXLXL 12tCLCL 4tCLCL tQVXH 10tCLCL 3tCLCL tXHQX 2tCLCL tCLCL tXHDX tCLCL tCLCL tXHDV 11tCLCL 3tCLCL ns ns ns ns ns ns ns ns ns ns MIN TYP MAX UNITS NOTES
EXPLANATION OF AC SYMBOLS
In an effort to remain compatible with the original 8051 family, this device specifies the same parameters as such devices, using the same symbols. For completeness, the following is an explanation of the symbols. t Time L Logic level low V Valid A Address I Instruction W WR signal C Clock X No longer a valid logic P PSEN D Input data level Q Output data H Logic level high Z Tristate R RD signal 34 of 44
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POWER CYCLE TIMING CHARACTERISTICS
PARAMETER Cycle Startup Time Power-on Reset Delay SYMBOL tCSU tPOR MIN TYP 1.8 MAX 65536 UNITS ms tCLCL NOTES 1 2
NOTES FOR POWER CYCLE TIMING:
1. Startup time for crystals varies with load capacitance and manufacturer. Time shown is for an 11.0592 MHz crystal manufactured by Fox. 2. Reset delay is a synchronous counter of crystal oscillations after crystal startup. At 33 MHz, this time is 1.99 ms.
EPROM PROGRAMMING AND VERIFICATION
PARAMETER Programming Voltage Programming Supply Current Oscillator Frequency Address Setup to PROG Low Address Hold after PROG Data Setup to PROG Low Data Hold after PROG Enable High to VPP VPP Setup to PROG Low VPP Hold after PROG
PROG
(21C to 27C; VCC=4.5V to 5.5V)
SYMBOL VPP IPP 1/tCLCL tAVGL tGHAX tDVGL tGHDX tEHSH tSHGL tGHSL tGLGH tAVQV tELQV tEHQZ tGHGL 0 10 4 48tCLCL 48tCLCL 48tCLCL 48tCLCL 48tCLCL 10 10 90 110 48tCLCL 48tCLCL 48tCLCL s s s s MIN 12.5 TYP MAX 13.0 50 6 UNITS V mA MHz NOTES 1
Width
Address to Data Valid Enable Low to Data Valid Data Float after Enable
PROG
High to PROG Low
NOTE:
1. All Voltages are referenced to ground.
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EXTERNAL PROGRAM MEMORY READ CYCLE
EXTERNAL DATA MEMORY READ CYCLE
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DATA MEMORY WRITE CYCLE
DATA MEMORY WRITE WITH STRETCH=1
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DATA MEMORY WRITE WITH STRETCH=2
EXTERNAL CLOCK DRIVE
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SERIAL PORT MODE 0 TIMING
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POWER CYCLE TIMING
EPROM PROGRAMMING AND VERIFICATION WAVEFORMS
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52-PIN PLCC
PKG DIM A A1 A2 B B1 c CH1 D D1 D2 E E1 E2 e1 N
52-PIN MIN 0.165 0.090 0.020 0.026 0.013 0.008 0.042 0.785 0.750 0.690 0.785 0.750 0.690 MAX 0.180 0.120 0.032 0.021 0.013 0.048 0.795 0.756 0.730 0.795 0.756 0.730
0.050 BSC 52 -
56-G4006-001
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52-PIN CER QUAD
PKG DIM A A1 B B1 c CH145 D D1 D2 E E1 E2 e1 N
52-PIN MIN 0.165 0.040 0.026 0.013 0.008 0.035 0.760 0.740 0.700 0.760 0.740 0.700 MAX 0.185 0.032 0.021 0.013 0.040 0.800 0.770 0.730 0.800 0.770 0.730
0.050 BSC 52 -
56-G4007-001
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52-PIN TQFP
PKG DIM A A1 A2 b c D D1 E E1 e L 0.45 11.80 MIN 0.05 0.95 0.25 0.09 11.80
52-PIN NOM 0.10 1.00 0.32 12.00 10.00 BSC 12.00 10.00 BSC 0.65 BSC 0.60 0.75 12.20 MAX 1.20 0.15 1.05 0.40 0.20 12.20
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DATA SHEET REVISION SUMMARY
The following represent the key differences between 02/20/97 and 07/07/98 version of the DS87C530 data sheet. Please review this summary carefully. 1. Add DS83C530 to data sheet. 2. Updated PMM operating current estimates. 3. Added note to clarify IIL specification. 4. Added note to prevent accidental corruption of Watchdog Timer count while changing counter length. 5. Changed IBAT specification to 1 A over extended temperature range. 6. Changed minimum oscillator frequency to 1 MHz when using external crystal. 7. Changed RST pulldown resistance from 170 k=to 200 k=maximum. 8. Corrected "Data memory write with stretch" diagrams to show falling edge of ALE coincident with rising edge of C3 clock. The following represent the key differences between 06/08/95 and 02/20/97 version of the DS87C530 data sheet. Please review this summary carefully. 1. Update ALE pin description. 2. Add note pertaining to erasure window. 3. Add note pertaining to internal MOVX SRAM. 4. Change Note 6 from RST=5.5V to RST=VCC. 5. Change Note 10 from RST=5.5V to RST=VCC. 6. Change serial port mode 0 timing diagram label from tQVXL to tQVXH. 7. Add information pertaining to 52-pin TQFP package.
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